linuxvoice about riscv hardware
Thanks, I think it's an interesting project. However I was saddened to read
"Although LowRISC is trying to make a fully open SoC, it won’t be able to completely avoid proprietary code from the first version. Alex Bradbury told us: “As for all this open source stuff, there are a whole bunch of lines that you can choose to draw. The lowest aim is for everything that you would implement in a hardware description language (like Verilog) to be fully open – so all the digital logic is fully open. [However,] it might be that in the initial case, we need to take on some closed source intellectual property for some IO controllers, because often the physical interface is very tightly integrated and tightly tied to the controller. It might just be too much engineering work for the first chip.”
While we do feel that it’s a bit of a shame that the initial SoC won’t be completely open, we understand the need to be pragmatic when bringing something as complicated as an SoC to market. Since the RAM will be in a separate chip, this closed source code will just be dealing with the interaction with that memory. This is something, Bradbury explained, that the team would like to open in future revisions."
Well, time will tell.
This is indeed sad, but also kinda in line with the goals and so could be seen as not being a compromise (from their point of view) because they're still delivering on what they wanted: The CPU. RISC V is only about making a CPU. Will the rest of said computer be free? It's hard to tell because the rest of the components are not specified by RISC V: Only the CPU is. A full computer has more than just the CPU (it needs a memory controller for one which that quote was talking about as well as other components.) If their goal were to make a complete computer free and not just a free CPU then maybe this might not have happened.
Right, good point! Sounds like they're interested in pursuing goals beyond the CPU as well.